Invention Grant
- Patent Title: Non-volatile semiconductor memory device
- Patent Title (中): 非易失性半导体存储器件
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Application No.: US13329553Application Date: 2011-12-19
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Publication No.: US08649224B2Publication Date: 2014-02-11
- Inventor: Masanobu Shirakawa , Hiroshi Sukegawa
- Applicant: Masanobu Shirakawa , Hiroshi Sukegawa
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2011-081836 20110401
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
A control circuit performs a read operation of reading data held in a memory-cell by supplying a selected word-line with a read voltage that is a voltage between the lower limit and the upper limit of a plurality of threshold-voltage distributions provided to the memory-cell. The control circuit also performs a verify operation of determining whether a write operation is completed by supplying a selected word-line with a verify voltage higher than the read voltage to read the memory cell. The control circuit then performs a data variation determination operation of determining whether the memory-cells connected to a selected word-line each have a threshold voltage equal to or less than a certain value to determine, from among the plurality of memory cells connected to the selected word-line, whether the number of memory cells where data variation has occurred is not less than a certain number.
Public/Granted literature
- US20120250420A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2012-10-04
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