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US08649240B2 Mechanism for peak power management in a memory 有权
记忆中峰值功率管理的机制

Mechanism for peak power management in a memory
Abstract:
A mechanism for managing peak power in a memory storage array that includes sub-array blocks may reduce the peak currents associated with read and write operations by staggering the wordline signal activation to each of the sub-array blocks. In particular, the wordline units within each sub-array block may generate the wordline signals to each sub-array block such that a read wordline signal of one sub-array block does not transition from one logic level to another logic level at the same time as the write wordline of another sub-array block. Further, the wordline units may generate the wordline signals to each sub-array block such that a read wordline of a given sub-array block does not transition from one logic level to another logic level at the same time as a read wordline signal of another sub-array block.
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