Invention Grant
- Patent Title: Method for detecting variance in semiconductor processes
- Patent Title (中): 检测半导体工艺方差的方法
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Application No.: US13170229Application Date: 2011-06-28
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Publication No.: US08649990B2Publication Date: 2014-02-11
- Inventor: Yij Chieh Chu , Chun Chi Chen , Yun-Zong Tian
- Applicant: Yij Chieh Chu , Chun Chi Chen , Yun-Zong Tian
- Applicant Address: TW Taoyuan County
- Assignee: Inotera Memories, Inc.
- Current Assignee: Inotera Memories, Inc.
- Current Assignee Address: TW Taoyuan County
- Agency: Rosenberg, Klein & Lee
- Priority: TW97125844A 20080709
- Main IPC: G06F19/00
- IPC: G06F19/00

Abstract:
A method of detecting variance by regression model has the following steps. Step 1 is preparing the FDC data and WAT data for analysis. Step 2 is figuring out what latent variable effect of WAT data by Factor Analysis Step 3 is utilizing Principal Component Analysis to reduce the number of FDC variables to a few independent principal components. Step 4 is demonstrating how the tools and FDC data affect WAT data by Analysis of covariance model, and constructing interrelationship among FDC, WAT and tools. The interrelationship can point out which parameter effect WAT significantly. By the method, when WAT abnormal situation happened, it is easier for engineers to trace where the problem is.
Public/Granted literature
- US20110257932A1 METHOD FOR DETECTING VARIANCE IN SEMICONDUCTOR PROCESSES Public/Granted day:2011-10-20
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