发明授权
US08652913B2 Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss
有权
在具有降低的硅/锗损失的晶体管中形成含硅/锗的漏/源区的方法
- 专利标题: Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss
- 专利标题(中): 在具有降低的硅/锗损失的晶体管中形成含硅/锗的漏/源区的方法
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申请号: US11778930申请日: 2007-07-17
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公开(公告)号: US08652913B2公开(公告)日: 2014-02-18
- 发明人: Andreas Gehring , Maciej Wiatr , Andy Wei , Thorsten Kammler , Roman Boschke , Casey Scott
- 申请人: Andreas Gehring , Maciej Wiatr , Andy Wei , Thorsten Kammler , Roman Boschke , Casey Scott
- 申请人地址: KY Grand Cayman
- 专利权人: GLOBALFOUNDRIES Inc.
- 当前专利权人: GLOBALFOUNDRIES Inc.
- 当前专利权人地址: KY Grand Cayman
- 代理机构: Amerson Law Firm, PLLC
- 优先权: DE102007004862 20070131
- 主分类号: H01L21/336
- IPC分类号: H01L21/336
摘要:
By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.
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