Invention Grant
- Patent Title: Digital equalizer for high-speed serial communications
- Patent Title (中): 数字均衡器,用于高速串行通信
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Application No.: US12117515Application Date: 2008-05-08
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Publication No.: US08654898B2Publication Date: 2014-02-18
- Inventor: William W. Bereza , Albert Vareljian , Rakesh H. Patel
- Applicant: William W. Bereza , Albert Vareljian , Rakesh H. Patel
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Ropes & Gray LLP
- Agent Jeffrey H. Ingerman
- Main IPC: H04L27/01
- IPC: H04L27/01

Abstract:
Incoming data at a high-speed serial receiver is digitized and then digital signal processing (DSP) techniques may be used to perform digital equalization. Such digital techniques may be used to correct various data anomalies. In particular, in a multi-channel system, where crosstalk may be of concern, knowledge of the characteristics of the other channels, or even the data on those channels, may allow crosstalk to be subtracted out. Knowledge of data channel geometries, particularly in the context of backplane transmissions, may allow echoes and reflections caused by connectors to be subtracted out. As data rates increase, fractional rate processing can be employed. For example, the analog-to-digital conversion can be performed at half-rate and then two DSPs can be used in parallel to maintain throughput at the higher initial clock rate. At even higher rates, quadrature techniques can allow analog-to-digital conversion at quarter-rate, with four DSPs used in parallel.
Public/Granted literature
- US20090279597A1 DIGITAL EQUALIZER FOR HIGH-SPEED SERIAL COMMUNICATIONS Public/Granted day:2009-11-12
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