Invention Grant
US08656072B2 Memory bus architecture for concurrently supporting volatile and non-volatile memory modules
有权
用于同时支持易失性和非易失性存储器模块的内存总线架构
- Patent Title: Memory bus architecture for concurrently supporting volatile and non-volatile memory modules
- Patent Title (中): 用于同时支持易失性和非易失性存储器模块的内存总线架构
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Application No.: US13236416Application Date: 2011-09-19
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Publication No.: US08656072B2Publication Date: 2014-02-18
- Inventor: Jonathan R. Hinkle , Paul Sweere
- Applicant: Jonathan R. Hinkle , Paul Sweere
- Applicant Address: US CA San Jose
- Assignee: Sanmina-SCI Corporation
- Current Assignee: Sanmina-SCI Corporation
- Current Assignee Address: US CA San Jose
- Agency: Loza & Loza, LLP
- Agent Julio M. Loza
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F5/00 ; H05K7/10 ; G06F13/20

Abstract:
A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus.
Public/Granted literature
- US20120159045A1 MEMORY BUS ARCHITECTURE FOR CONCURRENTLY SUPPORTING VOLATILE AND NON-VOLATILE MEMORY MODULES Public/Granted day:2012-06-21
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