发明授权
- 专利标题: System and method for implementing power integrity topology adapted for parametrically integrated environment
- 专利标题(中): 适用于参数集成环境的电源完整性拓扑的系统和方法
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申请号: US12979137申请日: 2010-12-27
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公开(公告)号: US08656329B1公开(公告)日: 2014-02-18
- 发明人: Taranjit Singh Kukal , Feras Al-Hawari , Dennis Nagle , Raymond Komow , Jilin Tan
- 申请人: Taranjit Singh Kukal , Feras Al-Hawari , Dennis Nagle , Raymond Komow , Jilin Tan
- 申请人地址: US CA San Jose
- 专利权人: Cadence Design Systems, Inc.
- 当前专利权人: Cadence Design Systems, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Rosenberg, Klein & Lee
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A system and method are provided for generating a programmably implemented model which emulates a power delivery network serving an integrated circuit (IC) core in an electronic system. The system and method generally comprise measures for establishing a power integrity (PI) topology including models for a voltage regulator module that generates at least one predetermined supply voltage level, and for a conductive power rail portion of the power delivery network (PDN). The system and method further comprise measures for interconnecting to the conductive power rail portion model a first behavioral model indicative of the current consumption characteristics of the IC core, and a second behavioral model indicative of the current consumption of an IO interface buffer driving an output signal of the electronic system.
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