Invention Grant
US08667675B2 Simultaneous and selective partitioning of via structures using plating resist
有权
使用电镀抗蚀剂同时选择性地分配通孔结构
- Patent Title: Simultaneous and selective partitioning of via structures using plating resist
- Patent Title (中): 使用电镀抗蚀剂同时选择性地分配通孔结构
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Application No.: US12190551Application Date: 2008-08-12
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Publication No.: US08667675B2Publication Date: 2014-03-11
- Inventor: George Dudnikov, Jr.
- Applicant: George Dudnikov, Jr.
- Applicant Address: US CA San Jose
- Assignee: Sanmina Sci Corporation
- Current Assignee: Sanmina Sci Corporation
- Current Assignee Address: US CA San Jose
- Agency: Loza & Loza, LLP
- Agent Julio M. Loza
- Main IPC: H01K3/10
- IPC: H01K3/10

Abstract:
Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.
Public/Granted literature
- US20080301934A1 Simultaneous and selective partitioning of via structures using plating resist Public/Granted day:2008-12-11
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