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US08671323B2 High throughput decoder architecture for low-density parity-check convolutional codes 有权
用于低密度奇偶校验卷积码的高吞吐量解码器架构

High throughput decoder architecture for low-density parity-check convolutional codes
摘要：
A Low-Density Parity-Check Convolutional Code (LPDCCC) decoder (10) for partial parallel decoding of low-density parity-check convolutional codes, the decoder having: a plurality of pipeline processors (11) to receive channel messages and edge-messages; each processor (11) having: a plurality of block processing units (BPUs) (13), each BPU (13) having a plurality of check node processors (CNPs) (14) to process check nodes that enter into the processor (11) and a plurality of variable node processors (VNPs) (15) to process variable nodes that are about to leave the processor (11); and a plurality of Random Access Memory (RAM) blocks (30) for dynamic message storage of the channel messages and the edge-messages; wherein in each processor (11), the VNPs (15) are directly connected to corresponding RAM blocks (30), and the CNPs (14) are directly connected to corresponding RAM blocks (30) such that the connections from the VNPs (15) and CNPs (14) to the corresponding RAM blocks (30) are pre-defined and fixed according to a parity-check matrix of an unterminated time-varying periodic LDPCCC.
摘要（中）：

一种用于低密度奇偶校验卷积码的部分并行解码的低密度奇偶校验卷积码（LPDCCC）解码器（10），所述解码器具有：多个流水线处理器（11），用于接收信道消息和边缘消息 ; 每个处理器（11）具有：多个块处理单元（BPU）（13），每个BPU（13）具有多个校验节点处理器（CNP）（14），用于处理进入处理器（11）的校验节点， 以及多个可变节点处理器（VNP）（15），用于处理即将离开处理器（11）的变量节点; 和用于信道消息和边缘消息的动态消息存储的多个随机存取存储器（RAM）块（30）; 其中在每个处理器（11）中，VNP（15）直接连接到对应的RAM块（30），并且CNP（14）直接连接到对应的RAM块（30），使得来自VNP（15）的连接 并且根据未终止的时变周期性LDPCCC的奇偶校验矩阵来预定义和固定到对应的RAM块（30）的CNP（14）。

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