利索-全球专利检索

  1. 登录
  2. 注册
发明授权
US08674244B2 Time difference adders, time difference accumulators, sigma-delta time-to-digital converters, digital phase locked loops and temperature sensors 有权
时差加法器，时差累加器，Σ-Δ时间数字转换器，数字锁相环和温度传感器

Time difference adders, time difference accumulators, sigma-delta time-to-digital converters, digital phase locked loops and temperature sensors
摘要：
A time difference adder included in a system-on-chip (SOC) includes a first register unit and a second register unit. The first register unit is configured to receive first and second input signals having a first time difference, and generate a first output signal in response to a first signal. The second register unit is configured to receive third and fourth input signals having a second time difference, and generate a second output signal having a third time difference with respect to the first output signal in response to the first signal. The third time difference corresponds to a sum of the first time difference and the second time difference.
摘要（中）：

包括在片上系统（SOC）中的时差加法器包括第一寄存器单元和第二寄存器单元。 第一寄存器单元被配置为接收具有第一时间差的第一和第二输入信号，并响应于第一信号产生第一输出信号。 第二寄存器单元被配置为接收具有第二时间差的第三和第四输入信号，并且响应于第一信号产生相对于第一输出信号具有第三时间差的第二输出信号。 第三时间差对应于第一时间差和第二时间差的和。

公开/授权文献
信息查询
Espacenet
0/0