- 专利标题: Gate structure in non-volatile memory device
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申请号: US13759195申请日: 2013-02-05
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公开(公告)号: US08674429B2公开(公告)日: 2014-03-18
- 发明人: Jang-Gn Yun , Jung-Dal Choi , Kwang-Soo Seol
- 申请人: Jang-Gn Yun , Jung-Dal Choi , Kwang-Soo Seol
- 申请人地址: KR Gyeonggi-do
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Gyeonggi-do
- 代理机构: Harness, Dickey & Pierce, P.L.C.
- 优先权: KR10-2012-0039915 20120417
- 主分类号: H01L21/02
- IPC分类号: H01L21/02
摘要:
A gate structure of a non-volatile memory device and a method of forming the same including a tunnel oxide layer pattern, a charge trap layer pattern, a blocking dielectric layer pattern having the uppermost layer including a material having a first dielectric constant greater than that of a material included in the tunnel oxide layer pattern, and first and second conductive layer patterns. The gate structure includes a first spacer to cover at least the sidewall of the second conductive layer pattern. The gate structure includes a second spacer covering the sidewall of the first spacer and the sidewall of the first conductive layer pattern and including a material having a second dielectric constant equal to or greater than the first dielectric constant. In the non-volatile memory device including the gate structure, erase saturation caused by back tunneling is reduced.
公开/授权文献
- US20130270624A1 GATE STRUCTURE IN NON-VOLATILE MEMORY DEVICE 公开/授权日:2013-10-17