发明授权
US08679927B2 Integration of non-volatile charge trap memory devices and logic CMOS devices
有权
集成非易失性电荷陷阱存储器件和逻辑CMOS器件
- 专利标题： Integration of non-volatile charge trap memory devices and logic CMOS devices
- 专利标题（中）： 集成非易失性电荷陷阱存储器件和逻辑CMOS器件
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申请号： US12185751申请日： 2008-08-04
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公开(公告)号： US08679927B2公开(公告)日： 2014-03-25
- 发明人: Krishnaswamy Ramkumar , Fredrick B. Jenne , Sagy Levy
- 申请人： Krishnaswamy Ramkumar , Fredrick B. Jenne , Sagy Levy
- 申请人地址： US CA San Jose
- 专利权人： Cypress Semiconductor Corporation
- 当前专利权人： Cypress Semiconductor Corporation
- 当前专利权人地址： US CA San Jose
- 主分类号： H01L29/792
- IPC分类号： H01L29/792
摘要：
A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.
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