Invention Grant
- Patent Title: Method for fabricating interconnecting lines inside via holes of semiconductor device
- Patent Title (中): 在半导体器件的通孔内部形成互连线的方法
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Application No.: US13416627Application Date: 2012-03-09
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Publication No.: US08679974B2Publication Date: 2014-03-25
- Inventor: Wei-leun Fang , Chia Han Lin , Feng Yu Lee
- Applicant: Wei-leun Fang , Chia Han Lin , Feng Yu Lee
- Applicant Address: TW Hsinchu
- Assignee: National Tsing Hua University
- Current Assignee: National Tsing Hua University
- Current Assignee Address: TW Hsinchu
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Priority: TW100147037A 20111219
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A method for fabricating interconnecting lines inside via holes of a semiconductor device comprises steps of providing a template having a receiving trench and a connection surface both on the same side of the template; filling an electric-conduction material into the receiving trench; connecting a substrate having at least one via hole with the connection surface to interconnect the via hole with the receiving trench; heating the electric-conduction material to a working temperature to liquefy a portion of the electric-conduction material and make it flows from the receiving trench into the via hole; and cooling the electric-conduction material to form an interconnecting line inside the via hole. The present invention fabricates interconnecting lines by a heat-forming method, which features simple steps and has advantages of shorter fabrication time, lower fabrication complexity, higher fabrication efficiency, higher yield and lower fabrication cost.
Public/Granted literature
- US20130157459A1 METHOD FOR FABRICATING INTERCONNECTING LINES INSIDE VIA HOLES OF SEMICONDUCTOR DEVICE Public/Granted day:2013-06-20
Information query
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