Invention Grant
US08685813B2 Method of integrating a charge-trapping gate stack into a CMOS flow
有权
将电荷捕获栅极堆叠集成到CMOS流中的方法
- Patent Title: Method of integrating a charge-trapping gate stack into a CMOS flow
- Patent Title (中): 将电荷捕获栅极堆叠集成到CMOS流中的方法
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Application No.: US13428201Application Date: 2012-03-23
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Publication No.: US08685813B2Publication Date: 2014-04-01
- Inventor: Krishnaswamy Ramkumar
- Applicant: Krishnaswamy Ramkumar
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
Embodiments of a method of integration of a non-volatile memory device into a MOS flow are described. Generally, the method includes: forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack; patterning the cap layer and the dielectric stack to form a gate stack of a memory device in a first region of the substrate and to remove the cap layer and the charge-trapping layer from a second region of the substrate; and performing an oxidation process to form a gate oxide of a MOS device overlying the surface of the substrate in the second region while simultaneously oxidizing the cap layer to form a blocking oxide overlying the charge-trapping layer. Other embodiments are also disclosed.
Public/Granted literature
- US20130210209A1 METHOD OF INTEGRATING A CHARGE-TRAPPING GATE STACK INTO A CMOS FLOW Public/Granted day:2013-08-15
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