Method of forming non-planar FET

Invention Grant

US08691651B2 Method of forming non-planar FET 有权

Title translation: 形成非平面FET的方法

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Patent Title: Method of forming non-planar FET
Patent Title (中): 形成非平面FET的方法
Application No.: US13218438

Application Date: 2011-08-25
Publication No.: US08691651B2

Publication Date: 2014-04-08
Inventor: Sheng-Huei Dai , Rai-Min Huang , Chen-Hua Tsai , Shih-Hung Tsai , Chien-Ting Lin
Applicant: Sheng-Huei Dai , Rai-Min Huang , Chen-Hua Tsai , Shih-Hung Tsai , Chien-Ting Lin
Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
Assignee: United Microelectronics Corp.
Current Assignee: United Microelectronics Corp.
Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
Agent Winston Hsu; Scott Margo
Main IPC: H01L21/8234
IPC: H01L21/8234 ; H01L21/336

Abstract:

A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.

Abstract(Chinese):

提供一种形成非平面FET的方法。提供基板。在衬底上限定有源区和周边区。在基板的有源区域中形成多个VSTI。去除每个VSTI的一部分以露出衬底的侧壁的一部分。然后，在衬底上形成导体层，然后将其图案化以在外围区域中形成平面FET栅极，并且在有源区域中同时形成非平面FET栅极。最后，源极/漏极区域形成在非平面FET栅极的两侧。

Public/Granted literature

US20130052781A1 Method of Forming Non-planar FET Public/Granted day:2013-02-28

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺