Invention Grant
US08691684B2 Layout and pad floor plan of power transistor for good performance of SPU and STOG
有权
功率晶体管的布局和焊盘平面图,实现了SPU和STOG的良好性能
- Patent Title: Layout and pad floor plan of power transistor for good performance of SPU and STOG
- Patent Title (中): 功率晶体管的布局和焊盘平面图,实现了SPU和STOG的良好性能
-
Application No.: US13906223Application Date: 2013-05-30
-
Publication No.: US08691684B2Publication Date: 2014-04-08
- Inventor: Guo Hua Zhong , Mei Yang
- Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
- Applicant Address: CN Shenzhen
- Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd.
- Current Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd.
- Current Assignee Address: CN Shenzhen
- Agency: Seed IP Law Group PLLC
- Priority: CN200910253051 20090930
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.
Public/Granted literature
- US20130267087A1 LAYOUT AND PAD FLOOR PLAN OF POWER TRANSISTOR FOR GOOD PERFORMANCE OF SPU AND STOG Public/Granted day:2013-10-10
Information query
IPC分类: