Invention Grant
US08691684B2 Layout and pad floor plan of power transistor for good performance of SPU and STOG 有权
功率晶体管的布局和焊盘平面图,实现了SPU和STOG的良好性能

Layout and pad floor plan of power transistor for good performance of SPU and STOG
Abstract:
A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.
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