Invention Grant
- Patent Title: Methods for fabricating integrated circuits having low resistance device contacts
- Patent Title (中): 制造具有低电阻器件触点的集成电路的方法
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Application No.: US13689839Application Date: 2012-11-30
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Publication No.: US08691689B1Publication Date: 2014-04-08
- Inventor: Paul R. Besser , Sean X. Lin , Valli Arunachalam
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
Methods for fabricating integrated circuits having low resistance device contacts are provided. One method includes depositing an ILD layer of insulating material overlying a device region that includes a metal silicide region. The ILD layer is etched to form a sidewall that defines a contact opening formed through the ILD layer exposing the metal silicide region. A liner is formed overlying the sidewall and the metal silicide region and defines an inner cavity in the contact opening. A copper layer is formed overlying the liner and at least partially filling the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.
Information query
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