Invention Grant
- Patent Title: Method of patterning for a semiconductor device
- Patent Title (中): 半导体器件的图案化方法
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Application No.: US13364119Application Date: 2012-02-01
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Publication No.: US08697537B2Publication Date: 2014-04-15
- Inventor: Chia Ying Lee , Chih-Yuan Ting , Jyu-Horng Shieh
- Applicant: Chia Ying Lee , Chih-Yuan Ting , Jyu-Horng Shieh
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/76
- IPC: H01L21/76

Abstract:
A method that includes forming a masking element on a semiconductor substrate and overlying a defined space. A first feature and a second feature are each formed on the semiconductor substrate. The space interposes the first and second features and extends from a first end of the first feature to a first end of the second feature. A third feature is then formed adjacent and substantially parallel the first and second features. The third feature extends at least from the first end of the first feature to the first end of the second feature.
Public/Granted literature
- US20130196481A1 METHOD OF PATTERNING FOR A SEMICONDUCTOR DEVICE Public/Granted day:2013-08-01
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