Invention Grant
- Patent Title: Bump structural designs to minimize package defects
- Patent Title (中): 凹凸结构设计,以尽量减少包装缺陷
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Application No.: US13362913Application Date: 2012-01-31
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Publication No.: US08698308B2Publication Date: 2014-04-15
- Inventor: Jing-Cheng Lin , Cheng-Lin Huang
- Applicant: Jing-Cheng Lin , Cheng-Lin Huang
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman & Ham, LLP
- Main IPC: H01L29/40
- IPC: H01L29/40

Abstract:
The mechanisms for forming bump structures enable forming bump structures between a chip and a substrate eliminating or reducing the risk of solder shorting, flux residue and voids in underfill. A lower limit can be established for a α ratio, defined by dividing the total height of copper posts in a bonded bump structure divided by the standoff of the bonded bump structure, to avoid shorting. A lower limit may also be established for standoff the chip package to avoid flux residue and underfill void formation. Further, aspect ratio of a copper post bump has a lower limit to avoid insufficient standoff and a higher limit due to manufacturing process limitation. By following proper bump design and process guidelines, yield and reliability of chip packages may be increases.
Public/Granted literature
- US20130193593A1 BUMP STRUCTURAL DESIGNS TO MINIMIZE PACKAGE DEFECTS Public/Granted day:2013-08-01
Information query
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