A cache memory apparatus is configured to include a data holding unit comprising a plurality of ways that has a plurality of cache lines; an alternation data register to hold data in one line of the cache lines or in a part of the cache lines; an alternation address register to hold an index address that indicates a faulty cache line and a part in which the fault has occurred in the faulty cache line; an alternation way register to hold information of a way including the part having a fault; an address match circuit comparing, when an access is performed to the data holding unit, an index address and the index address held by the alternation address register; and a way match circuit comparing, when an access is performed to the data holding unit, way information used for the access and way information held by the alternation way register.