A disclosed semiconductor design support apparatus reads circuit description information and generates information required for delay adjustment. The semiconductor design support apparatus includes a logic simulation unit configured to perform logic simulation based on the circuit description information and output logic simulation result information; a latency information acquiring unit configured to acquire, from the logic simulation result information, latency information relating to signals at a signal junction, the signals being output from multiple blocks; an adjustment latency calculating unit configured to calculate, from the latency information, adjustment latency information required for the delay adjustment; and an adjustment delay information generating unit configured to generate, from the adjustment latency information, adjustment delay information required for the delay adjustment.