Invention Grant
US08704226B2 Three-dimensional integrated circuit having redundant relief structure for chip bonding section
有权
具有用于芯片接合部分的冗余浮雕结构的三维集成电路
- Patent Title: Three-dimensional integrated circuit having redundant relief structure for chip bonding section
- Patent Title (中): 具有用于芯片接合部分的冗余浮雕结构的三维集成电路
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Application No.: US13812011Application Date: 2012-01-11
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Publication No.: US08704226B2Publication Date: 2014-04-22
- Inventor: Takashi Morimoto , Takashi Hashimoto
- Applicant: Takashi Morimoto , Takashi Hashimoto
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: JP2011-089370 20110413
- International Application: PCT/JP2012/000123 WO 20120111
- International Announcement: WO2012/140810 WO 20121018
- Main IPC: H01L23/58
- IPC: H01L23/58

Abstract:
A chip is layered on a rewiring member. A plurality of connecting members and a plurality of redundant connecting members are arranged in the chip, and electrically connect the chip to the rewiring member. Redundant circuits are embedded in each of the rewiring member and the chip. When one of the connecting members is faulty, the redundant circuits cause one of the redundant connecting members to transmit a signal between the rewiring member and the chip, instead of the faulty connecting member. The connecting members have first and second subsets arranged in first and second regions, respectively. A distance between the rewiring member and the chip exceeds a predetermined threshold value in the first region in contrast to the second region. The first subset has a higher proportion of connecting members that the redundant circuits can replace with a subset of the redundant connecting members than the second subset.
Public/Granted literature
- US20130127028A1 THREE-DIMENSIONAL INTEGRATED CIRCUIT HAVING REDUNDANT RELIEF STRUCTURE FOR CHIP BONDING SECTION Public/Granted day:2013-05-23
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