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发明授权
US08704226B2 Three-dimensional integrated circuit having redundant relief structure for chip bonding section 有权
具有用于芯片接合部分的冗余浮雕结构的三维集成电路

Three-dimensional integrated circuit having redundant relief structure for chip bonding section
摘要：
A chip is layered on a rewiring member. A plurality of connecting members and a plurality of redundant connecting members are arranged in the chip, and electrically connect the chip to the rewiring member. Redundant circuits are embedded in each of the rewiring member and the chip. When one of the connecting members is faulty, the redundant circuits cause one of the redundant connecting members to transmit a signal between the rewiring member and the chip, instead of the faulty connecting member. The connecting members have first and second subsets arranged in first and second regions, respectively. A distance between the rewiring member and the chip exceeds a predetermined threshold value in the first region in contrast to the second region. The first subset has a higher proportion of connecting members that the redundant circuits can replace with a subset of the redundant connecting members than the second subset.
摘要（中）：

芯片层叠在重新布线构件上。 多个连接构件和多个冗余连接构件布置在芯片中，并将芯片电连接到重新布线构件。 冗余电路嵌入在每个重新布线构件和芯片中。 当其中一个连接构件故障时，冗余电路使冗余连接构件中的一个在重新布线构件和芯片之间传递信号，而不是错误的连接构件。 连接构件具有分别布置在第一和第二区域中的第一和第二子集。 与第二区域相比，重新布线构件和芯片之间的距离超过了第一区域中的预定阈值。 第一子集具有较高比例的连接构件，冗余电路可以用冗余连接构件的子集替代第二子集。

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