Invention Grant
- Patent Title: Decoder architecture systems, apparatus and methods
- Patent Title (中): 解码器架构系统，设备和方法
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Application No.: US11093732Application Date: 2005-03-30
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Publication No.: US08705632B2Publication Date: 2014-04-22
- Inventor: Eric F. Vannerson , Kalpesh D. Mehta , Louis A. Lippincott
- Applicant: Eric F. Vannerson , Kalpesh D. Mehta , Louis A. Lippincott
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: H04N7/12
- IPC: H04N7/12
Abstract:
An apparatus includes a decoder to receive a compressed bit stream that is based on a coding standard. The decoder includes a hardware accelerator to decode a part of the compressed bit stream that is based on an operation that is common across multiple coding standards that includes the coding standard. The decoder also includes a programmable element to decode a part of the compressed bit stream that is based on an operation that is specific to the coding standard.
Public/Granted literature
- US20060222000A1 Decoder architecture systems, apparatus and methods Public/Granted day:2006-10-05
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