Invention Grant
US08722471B2 Method for forming a via contacting several levels of semiconductor layers
有权
用于形成接触几层半导体层的通孔的方法
- Patent Title: Method for forming a via contacting several levels of semiconductor layers
- Patent Title (中): 用于形成接触几层半导体层的通孔的方法
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Application No.: US13748126Application Date: 2013-01-23
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Publication No.: US08722471B2Publication Date: 2014-05-13
- Inventor: Perrine Batude , Yves Morand
- Applicant: STMicroelectronics S.A. , Commissariat à l'Énergie Atomique et aux
- Applicant Address: FR Montrouge FR Paris
- Assignee: STMicroelectronics S.A.,Commissariat à l'Énergie Atomique et aux Énergies Alternatives
- Current Assignee: STMicroelectronics S.A.,Commissariat à l'Énergie Atomique et aux Énergies Alternatives
- Current Assignee Address: FR Montrouge FR Paris
- Agency: Wolf, Greenfield & Sacks, P.C.
- Priority: FR1250884 20120131
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material.
Public/Granted literature
- US20130196500A1 METHOD FOR FORMING A VIA CONTACTING SEVERAL LEVELS OF SEMICONDUCTOR LAYERS Public/Granted day:2013-08-01
Information query
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