Invention Grant
- Patent Title: Double patterning method for semiconductor devices
- Patent Title (中): 半导体器件的双重图案化方法
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Application No.: US13421606Application Date: 2012-03-15
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Publication No.: US08722541B2Publication Date: 2014-05-13
- Inventor: Chih-Han Lin
- Applicant: Chih-Han Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/302
- IPC: H01L21/302

Abstract:
A method of fabricating a semiconductor device is disclosed. The exemplary method includes providing a substrate including a device layer and a sacrificial layer formed over the device layer and patterning the sacrificial layer thereby defining a cut pattern. The cut pattern of the sacrificial layer having an initial width. The method further includes depositing a mask layer over the device layer and over the cut pattern of the sacrificial layer. The method further includes patterning the mask layer thereby defining a line pattern including first and second portions separated by the cut pattern of the sacrificial layer and selectively removing the cut pattern of the sacrificial layer thereby forming a gap that separates the first and second portions of the line pattern of the mask layer. The method further includes patterning the device layer using the first and second portions of the line pattern of the mask layer.
Public/Granted literature
- US20130244430A1 Double Patterning Method for Semiconductor Devices Public/Granted day:2013-09-19
Information query
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