发明授权
- 专利标题: Checksum verification accelerator
- 专利标题(中): 校验和验证加速器
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申请号: US13302688申请日: 2011-11-22
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公开(公告)号: US08726132B2公开(公告)日: 2014-05-13
- 发明人: Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
- 申请人: Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Brevetto Law Group
- 优先权: EP10306409 20101214
- 主分类号: H03M13/00
- IPC分类号: H03M13/00
摘要:
Disclosed is a method and system for validating a data packet by a network processor supporting a first network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet; identifies a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The system produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The system validates the data packet by comparing the data packet checksum to the second checksum.
公开/授权文献
- US20120151307A1 CHECKSUM VERIFICATION ACCELERATOR 公开/授权日:2012-06-14
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