Invention Grant
- Patent Title: Scheduling in a multicore processor
- Patent Title (中): 在多核处理器中进行调度
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Application No.: US11540146Application Date: 2006-09-29
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Publication No.: US08732439B2Publication Date: 2014-05-20
- Inventor: Mark D. Lippett
- Applicant: Mark D. Lippett
- Applicant Address: US CA Mountain View JP Kanagawa
- Assignee: Synopsys, Inc.,Fujitsu Semiconductor Limited
- Current Assignee: Synopsys, Inc.,Fujitsu Semiconductor Limited
- Current Assignee Address: US CA Mountain View JP Kanagawa
- Agency: Fenwick & West LLP
- Priority: GB0519981.5 20050930
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/40 ; G06F15/00

Abstract:
A method and computer-usable medium including instructions for performing a method for scheduling executable transactions within a multicore processor comprising a plurality of processor elements. The method includes listing, using at least one distribution queue, a portion of the executable transactions in order of eligibility for execution. A plurality of executable transaction schedulers are provided, wherein each executable transaction scheduler includes a scheduling process for determining a most eligible executable transaction for execution from at least one candidate executable transaction ready for execution. The executable transaction schedulers are linked together to provide a multilevel scheduler. The most eligible executable transaction is output from the multilevel scheduler to the at least one distribution queue.
Public/Granted literature
- US20070220517A1 Scheduling in a multicore processor Public/Granted day:2007-09-20
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