Disclosed are a method, non-transitory medium, and system of a tunable design of an Ethernet region of an integrated circuit (IC). In one embodiment, a method comprises modeling a design abstraction of an Ethernet sub-circuit of an integrated circuit as a register transfer level (RTL) code within a data processing device, wherein a first stage of sequential logic in the RTL code is associated with a first stage of combinational logic in the RTL code. The method further comprises implementing, through a processor and based on a timing parameter input into a synthesis tool associated with the RTL code, a selective bypass or a selective enablement of the first stage of sequential logic. Still further, the method comprises synthesizing, through the processor, a netlist from the RTL code, wherein the first stage of sequential logic is sequentially bypassed or sequentially enabled.