Invention Grant
- Patent Title: Stacked ESD clamp with reduced variation in clamp voltage
- Patent Title (中): 堆叠的ESD钳位钳位电压变化较小
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Application No.: US14073611Application Date: 2013-11-06
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Publication No.: US08749024B2Publication Date: 2014-06-10
- Inventor: Sameer Pendharkar , Marie Denison , Yongxi Zhang
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L27/082
- IPC: H01L27/082
Abstract:
An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.
Public/Granted literature
- US20140061859A1 STACKED ESD CLAMP WITH REDUCED VARIATION IN CLAMP VOLTAGE Public/Granted day:2014-03-06
Information query
IPC分类:
