An apparatus calculates a delay time of nets within a circuit included in design data by a processing unit. The processing unit performs a process that includes selecting a first calculation to calculate the delay time of a net when the net satisfies a first condition, when the first calculation is not selected by the selecting, selecting the first or second calculation to calculate the delay time of the net, depending on whether the net satisfies a second condition, and calculating the delay time of the net by the first or second calculation selected by the selecting.