Invention Grant
US08759907B2 Memory device having buried bit line and vertical transistor and fabrication method thereof
有权
具有掩埋位线和垂直晶体管的存储器件及其制造方法
- Patent Title: Memory device having buried bit line and vertical transistor and fabrication method thereof
- Patent Title (中): 具有掩埋位线和垂直晶体管的存储器件及其制造方法
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Application No.: US13094796Application Date: 2011-04-26
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Publication No.: US08759907B2Publication Date: 2014-06-24
- Inventor: Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
- Applicant: Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
- Applicant Address: TW Kueishan, Tao-Yuan Hsien
- Assignee: Nanya Technology Corp.
- Current Assignee: Nanya Technology Corp.
- Current Assignee Address: TW Kueishan, Tao-Yuan Hsien
- Agent Winston Hsu; Scott Margo
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/336 ; H01L27/108 ; H01L29/66
Abstract:
A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.
Public/Granted literature
- US20120273874A1 MEMORY DEVICE HAVING BURIED BIT LINE AND VERTICAL TRANSISTOR AND FABRICATION METHOD THEREOF Public/Granted day:2012-11-01
Information query
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