A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.