发明授权
- 专利标题: Multilevel DRAM
- 专利标题(中): 多级DRAM
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申请号: US13578498申请日: 2010-12-01
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公开(公告)号: US08773925B2公开(公告)日: 2014-07-08
- 发明人: Yoshihito Koya , Brent Haukness
- 申请人: Yoshihito Koya , Brent Haukness
- 申请人地址: US CA Sunnyvale
- 专利权人: Rambus Inc.
- 当前专利权人: Rambus Inc.
- 当前专利权人地址: US CA Sunnyvale
- 代理机构: Silicon Edge Law Group LLP
- 代理商 Arthur J. Behiel
- 国际申请: PCT/US2010/058533 WO 20101201
- 国际公布: WO2011/106054 WO 20110901
- 主分类号: G11C7/10
- IPC分类号: G11C7/10
摘要:
A multi-level dynamic random-access memory (MLDRAM) represents an original bit combination of more than one bit using a cell voltage stored in a single memory cell. The cell voltage is in one of a number of discrete analog voltage ranges each corresponding to a respective one of the possible values of the bit combination. In reading a selected memory cell, stored charge is conveyed via a local bitline to a preamplifier. The preamplifier amplifies the signal on the local bitline and drives a global bitline with an analog signal representative of the stored voltage. A digitizer converts the analog signal on the global bitline into a read bit combination. The read bit combination is then moved to a data cache over the global bitline. The data cache writes an analog voltage back to the memory cell to write a new value or restore data destroyed in reading the cell.
公开/授权文献
- US20120314484A1 Multilevel DRAM 公开/授权日:2012-12-13