发明授权
US08774228B2 Timing recovery method and apparatus for an input/output bus with link redundancy
有权
具有链路冗余的输入/输出总线的定时恢复方法和装置
- 专利标题: Timing recovery method and apparatus for an input/output bus with link redundancy
- 专利标题(中): 具有链路冗余的输入/输出总线的定时恢复方法和装置
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申请号: US13157968申请日: 2011-06-10
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公开(公告)号: US08774228B2公开(公告)日: 2014-07-08
- 发明人: John F. Bulzacchelli , Timothy O. Dickson , Daniel J. Friedman , Yong Liu , Sergey V. Rylov
- 申请人: John F. Bulzacchelli , Timothy O. Dickson , Daniel J. Friedman , Yong Liu , Sergey V. Rylov
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Tutunjian & Bitetto P.C.
- 代理商 Anne V. Dougherty
- 主分类号: H04J3/06
- IPC分类号: H04J3/06
摘要:
Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.
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