发明授权
US08782456B2 Dynamic and idle power reduction sequence using recombinant clock and power gating
有权
使用重组时钟和电源门控的动态和空闲功率降低序列
- 专利标题： Dynamic and idle power reduction sequence using recombinant clock and power gating
- 专利标题（中）： 使用重组时钟和电源门控的动态和空闲功率降低序列
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申请号： US12978452申请日： 2010-12-24
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公开(公告)号： US08782456B2公开(公告)日： 2014-07-15
- 发明人: Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
- 申请人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Caven & Aghevli LLC
- 主分类号： G06F1/32
- IPC分类号： G06F1/32
摘要：
Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.
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