Invention Grant
- Patent Title: Structure for integrated circuit alignment
- Patent Title (中): 集成电路对准的结构
-
Application No.: US12619460Application Date: 2009-11-16
-
Publication No.: US08786054B2Publication Date: 2014-07-22
- Inventor: Yu-Chyi Harn , Sophia Wang , Chun-Hung Lin , Hsien-Wei Chen , Ming-Yen Chiu
- Applicant: Yu-Chyi Harn , Sophia Wang , Chun-Hung Lin , Hsien-Wei Chen , Ming-Yen Chiu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
A method and device for pattern alignment are disclosed. The device can include an exposure field; a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and a die alignment mark disposed between the seal ring region and the corner stress relief region.
Public/Granted literature
- US20110115057A1 DESIGN STRUCTURE FOR INTEGRATED CIRCUIT ALIGNMENT Public/Granted day:2011-05-19
Information query
IPC分类:
