Invention Grant
US08787059B1 Cascaded content addressable memory array having multiple row segment activation
有权
具有多个行段激活的级联内容可寻址存储器阵列
- Patent Title: Cascaded content addressable memory array having multiple row segment activation
- Patent Title (中): 具有多个行段激活的级联内容可寻址存储器阵列
-
Application No.: US13311301Application Date: 2011-12-05
-
Publication No.: US08787059B1Publication Date: 2014-07-22
- Inventor: Vinay Iyengar
- Applicant: Vinay Iyengar
- Applicant Address: US CA Irvine
- Assignee: NetLogic Microsystems, Inc.
- Current Assignee: NetLogic Microsystems, Inc.
- Current Assignee Address: US CA Irvine
- Agency: Sterne, Kessler, Goldstein & Fox PLLC
- Main IPC: G11C15/00
- IPC: G11C15/00 ; G11C15/04 ; G11C7/10 ; G06F17/30

Abstract:
A content addressable memory (CAM) device has an array including a plurality of CAM rows that are partitioned into row segments, wherein a respective row includes a first row segment including a number of first CAM cells coupled to a first match line segment, a second row segment including a number of second CAM cells coupled to a second match line segment, and a circuit to selectively pre-charge the first match line segment in response to a value indicating whether data stored in the first row segment of the respective row is the same as data stored in the first row segment of another row. Power consumption can be reduced during compare operations in which the first row segment of another row that stores the same data as the first row segment of the respective row is not enabled.
Information query