Invention Grant
- Patent Title: Skewed partial column input/output floorplan
- Patent Title (中): 偏斜的部分列输入/输出平面图
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Application No.: US13601894Application Date: 2012-08-31
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Publication No.: US08791573B1Publication Date: 2014-07-29
- Inventor: Hui Liu , Christopher F. Lane , Arifur Rahman , Jianming Huang
- Applicant: Hui Liu , Christopher F. Lane , Arifur Rahman , Jianming Huang
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Weaver Austin Villeneuve & Sampson LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; G06F17/50

Abstract:
Techniques and mechanisms for providing embedded Input/Output (IO) blocks in a floor plan of a semiconductor device are provided, where the embedded IO blocks constitute partial columns (i.e., they do not extend from the bottom through to the top of the semiconductor device). In some embodiments, the partial column IO banks are skewed away from one another. In some embodiments, the partial column IO banks are located away from the center of the semiconductor device. Techniques and mechanisms for implementing symmetrical package routing using skewed partial column IO banks are also provided.
Information query
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