A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit. The m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits.