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US08796859B2 Multilayer interconnect structure and method for integrated circuits 有权
集成电路的多层互连结构和方法

Multilayer interconnect structure and method for integrated circuits
Abstract:
A multilayer interconnect structure is formed by, providing a substrate (40) having thereon a first dielectric (50, 27) for supporting a multi-layer interconnection (39) having lower conductor MN (22, 23), upper conductor MN+1 (34, 35), dielectric interlayer (DIL) (68) and interconnecting via conductor VN+1/N (36, 36′). The lower conductor MN (22, 23) has a first upper surface (61) located in a recess below a second upper surface (56) of the first dielectric (50, 27). The DIL (68) is formed above the first (61) and second (56) surfaces. A cavity (1263) is etched through the DIL (68) from a desired location (122) of the upper conductor MN+1 (34), exposing the first surface (61). The cavity (1263) is filled with a further electrical conductor (80) to form the upper conductor MN+1 (34) and the connecting via conductor VN+1/N (36, 36′) making electrical contact with the first upper surface (61). A critical dimension (32, 37) between others (23) of lower conductors MN (22, 23) and the via conductor VN+1/N (36, 36′) is lengthened. Leakage current and electro-migration there-between are reduced.
Abstract(Chinese):

多层互连结构通过提供一种衬底（40）形成，衬底（40）上具有第一电介质（50,27），用于支撑具有下导体MN（22,23），上导体MN + 1（ 34,35），电介质中间层（DIL）（68），并通过导体VN + 1 / N（36,36'）互连。 下导体MN（22,23）具有位于第一电介质（50,27）的第二上表面（56）下方的凹部中的第一上表面（61）。 DIL（68）形成在第一（61）和第二（56）表面上方。 通过DIL（68）从上导体MN + 1（34）的期望位置（122）蚀刻空腔（1263），露出第一表面（61）。 空腔（1263）填充有另外的电导体（80）以形成上导体MN + 1（34），并且连接通孔导体VN + 1 / N（36,36'）与第一上表面 （61）。 下导体MN（22,23）和通孔导体VN + 1 / N（36,36'）的其他（23）之间的临界尺寸（32,37）被延长。 泄漏电流和电迁移减少。

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