发明授权
- 专利标题： High performance CMOS transistors using PMD liner stress
- 专利标题（中）： 使用PMD衬垫应力的高性能CMOS晶体管
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申请号： US11670192申请日： 2007-02-01
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公开(公告)号： US08809141B2公开(公告)日： 2014-08-19
- 发明人: Haowen Bu , Rajesh Khamankar , Douglas T. Grider
- 申请人： Haowen Bu , Rajesh Khamankar , Douglas T. Grider
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Jacqueline J. Garner; Frederick J. Telecky, Jr.
- 主分类号： H01L29/739
- IPC分类号： H01L29/739
摘要：
A silicon nitrate layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.
公开/授权文献
- US20070128806A1 High performance CMOS transistors using PMD liner stress 公开/授权日：2007-06-07
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