Disclosed herein is a semiconductor integrated circuit including: a clamp MOS transistor having a drain region and a source region connected to a power source wiring and a grounding wiring, respectively, and causing a surge current to flow through a channel path and a bipolar path between the drain region and the source region; a first trigger circuit portion provided between the power source wiring and the grounding wiring, connected at an output terminal thereof to a gate terminal of the clamp MOS transistor, and controlling switching for the channel path; a second trigger circuit portion provided between the power source wiring and the grounding wiring, connected at an output terminal thereof to a well region of the clamp MOS transistor, and controlling switching for the bipolar path; and an internal circuit connected to each of the power source wiring and the grounding wiring.