One embodiment relates an apparatus which includes a plurality of local synchronous divider circuits, each local synchronous divider circuit being configured to receive a serial clock signal and a reset signal and generate a local clock signal. The apparatus further includes a clock distribution network configured to distribute the serial clock signal to the plurality of local synchronous divider circuits and a signal distribution network configured to distribute the reset signal to the plurality of local synchronous divider circuits. Another embodiment relates to a method of distributing a serial clock signal and a reset signal to a plurality of local synchronous divider circuits and generating a local clock signal at each of the plurality of local synchronous divider circuits. Other embodiments, aspects, and features are also disclosed.