Invention Grant
- Patent Title: Jitter reduction in high speed low core voltage level shifter
- Patent Title (中): 高速低电压电平转换器的抖动降低
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Application No.: US13494188Application Date: 2012-06-12
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Publication No.: US08816748B2Publication Date: 2014-08-26
- Inventor: Pankaj Kumar , Pramod Parameswaran , Makeshwar Kothandaraman
- Applicant: Pankaj Kumar , Pramod Parameswaran , Makeshwar Kothandaraman
- Applicant Address: US CA San Jose
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA San Jose
- Agency: Christopher P. Maiorana, PC
- Main IPC: H03L5/00
- IPC: H03L5/00

Abstract:
An apparatus comprising a level shifter circuit and a control circuit. The level shifter circuit may be configured to generate a differential output in response to (i) a first differential input, (ii) a second differential input and (iii) a first supply. The level shifter circuit comprises a first pull down transistor pair operating with the first supply. The control circuit may be configured to generate the second differential input in response to (i) the first differential input and (ii) a second supply. The control circuit generally comprises a second pull down transistor pair operating with the second supply. The first supply has a higher voltage than the second supply.
Public/Granted literature
- US20130328611A1 JITTER REDUCTION IN HIGH SPEED LOW CORE VOLTAGE LEVEL SHIFTER Public/Granted day:2013-12-12
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