Invention Grant
US08817711B2 Method and system for concurrently locating systematic bits and parity bits in physical channel memory to increase HARQ processing speed in 3GPP CPC system
有权
用于同时定位物理信道存储器中的系统位和奇偶校验位的方法和系统，以增加3GPP CPC系统中的HARQ处理速度
- Patent Title: Method and system for concurrently locating systematic bits and parity bits in physical channel memory to increase HARQ processing speed in 3GPP CPC system
- Patent Title (中): 用于同时定位物理信道存储器中的系统位和奇偶校验位的方法和系统，以增加3GPP CPC系统中的HARQ处理速度
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Application No.: US12768486Application Date: 2010-04-27
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Publication No.: US08817711B2Publication Date: 2014-08-26
- Inventor: Simon Baker
- Applicant: Simon Baker
- Applicant Address: US CA Irvine
- Assignee: Broadcom Corporation
- Current Assignee: Broadcom Corporation
- Current Assignee Address: US CA Irvine
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H04J1/16
- IPC: H04J1/16
Abstract:
A UE receives a HS-PDSCH transmission from a base station and concurrently performs rate matching on systematic bits and parity bits (parity 1 bits, parity 2 bits) of the received HS-PDSCH transmission. The systematic bits and parity bits are buffered in a CPC circular buffer to support HARQ processing in a HS-SCCH-less operation of the base station. Memory locations are computed for the systematic bits and the parity bits according to corresponding transmission parameters such as, for example, redundancy version, number of systematic bits and/or number of physical channels. The systematic bits and the parity bits are stored in the corresponding computed memory locations of the CPC circular buffer. At least a portion of the stored systematic bits and parity bits are concurrently generated based on corresponding transmission parameters from the CPC circular buffer per request to support concurrent rate matching on systematic bits and parity bits.
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