Invention Grant
US08819342B2 Methods and apparatus for managing page crossing instructions with different cacheability
有权
用于管理具有不同缓存性能的页面交叉指令的方法和装置
- Patent Title: Methods and apparatus for managing page crossing instructions with different cacheability
- Patent Title (中): 用于管理具有不同缓存性能的页面交叉指令的方法和装置
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Application No.: US13626916Application Date: 2012-09-26
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Publication No.: US08819342B2Publication Date: 2014-08-26
- Inventor: Leslie Mark DeBruyne , James Norris Dieffenderfer , Michael Scott Mcilvaine , Brian Michael Stempel
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Peter Michael Kamarchik; Nicholas J. Pauley; Joseph Agusta
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F9/38

Abstract:
An instruction in an instruction cache line having a first portion that is cacheable, a second portion that is from a page that is non-cacheable, and crosses a cache line is prevented from executing from the instruction cache. An attribute associated with the non-cacheable second portion is tracked separately from the attributes of the rest of the instructions in the cache line. If the page crossing instruction is reached for execution, the page crossing instruction and instructions following are flushed and a non-cacheable request is made to memory for at least the second portion. Once the second portion is received, the whole page crossing instruction is reconstructed from the first portion saved in the previous fetch group. The page crossing instruction or portion thereof is returned with the proper attribute for a non-cached fetched instruction and the reconstructed instruction can be executed without being cached.
Public/Granted literature
- US20140089598A1 METHODS AND APPARATUS FOR MANAGING PAGE CROSSING INSTRUCTIONS WITH DIFFERENT CACHEABILITY Public/Granted day:2014-03-27
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