An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to read and write data through a plurality of input/output lines. The second circuit may include a plurality of sections. Each section may be configured to present a control signal to a load output line and receive a feedback of the control signal through a load input line. The load input line and the load output line of each of the sections may be connected to a load circuit configured to match a respective memory load connected to each of the plurality of input/output lines.