Invention Grant
US08822293B2 Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices
有权
自对准晕圈/凹穴注入，用于减少MOS器件中的漏电和源极/漏极电阻
- Patent Title: Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices
- Patent Title (中): 自对准晕圈/凹穴注入，用于减少MOS器件中的漏电和源极/漏极电阻
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Application No.: US12048119Application Date: 2008-03-13
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Publication No.: US08822293B2Publication Date: 2014-09-02
- Inventor: Chen-Hua Yu , Yihang Chiu , Shu-Tine Yang , Jyh-Cherng Sheu , Chu-Yun Fu , Cheng-Tung Lin
- Applicant: Chen-Hua Yu , Yihang Chiu , Shu-Tine Yang , Jyh-Cherng Sheu , Chu-Yun Fu , Cheng-Tung Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/78 ; H01L21/265 ; H01L29/66 ; H01L29/165
Abstract:
A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation.
Public/Granted literature
- US20090233410A1 Self-Aligned Halo/Pocket Implantation for Reducing Leakage and Source/Drain Resistance in MOS Devices Public/Granted day:2009-09-17
Information query
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