Invention Grant
- Patent Title: Semiconductor structure and method for manufacturing the same
- Patent Title (中): 半导体结构及其制造方法
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Application No.: US13380612Application Date: 2011-04-18
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Publication No.: US08822334B2Publication Date: 2014-09-02
- Inventor: Haizhou Yin , Jun Luo , Zhijiong Luo , Huilong Zhu
- Applicant: Haizhou Yin , Jun Luo , Zhijiong Luo , Huilong Zhu
- Applicant Address: CN Beijing
- Assignee: The Institute of Microelectronics, Chinese Academy of Science
- Current Assignee: The Institute of Microelectronics, Chinese Academy of Science
- Current Assignee Address: CN Beijing
- Agency: Morgan, Lewis & Bockius LLP
- Priority: CN201010572616 20101203
- International Application: PCT/CN2011/072917 WO 20110418
- International Announcement: WO2012/071843 WO 20120607
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L29/45 ; H01L21/285 ; H01L29/66

Abstract:
A method for manufacturing a semiconductor structure comprises: providing a substrate (100) on which a dummy gate stack is formed, forming a spacer (240) at sidewalls of the dummy gate stack, and forming a source/drain region (110) and a source/drain extension region (111) at both sides of the dummy gate stack; removing at least part of the spacer (240), to expose at least part of the source/drain extension region (111); forming a contact layer (112) on the source/drain region (110) and the exposed source/drain extension region (111), the contact layer (112) being [made of] one of CoSi2, NiSi and Ni(Pt)Si2-y or combinations thereof, and a thickness of the contact layer (112) being less than 10 nm. Correspondingly, the present invention further provides a semiconductor structure which is beneficial to reducing contact resistance and can maintain excellent performance in a subsequent high temperature process.
Public/Granted literature
- US20120217589A1 Semiconductor structure and method for manufacturing the same Public/Granted day:2012-08-30
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